Page History

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• virtual evg. (should only require gui tweaks. check with ILA)
• how to handle the git large files
• get rid of gui
  • gui fully removed,
  • still need to make smart and stream line
• programmable event-code & trigger delay (axi bus)
• emulate epix model (send timestamp to front-end board. time stamp should be at the beginning of image packet.).  later:  maybe this isn't necessary because in future we would support camlink-over-fiber cameras with no front-end board?
• save hdf5
• full/deca mode (only 8 bit for deca or full)
• get test stand in 901 working
• start with Matt matched filter algorithm or Abdullah algorithm
• send results as udp packets
• is 8-bits OK for deca?
• understand how system behaves at high rates (do we drop frames? timestamps correct?)
• put in a fifo for timestamps?
• difference kc705  revisions 1.1 vs 1.2.:  no significant difference according to https://www.xilinx.com/support/answers/59751.html.  Either an FMC problem, or subtle timing issue, or need to specify board rev somehow when synthesizing?
• new front-end boards
  
• touch base with Ryan on code structure issues
• prepare for running in LCLS-I?  If yes:
  • spy on the timestamp multicasts in software (maybe not necessary)
  • take real pictures with lens from Ryan
  • trigger delay and event-code programmable via AXI
  • eliminate gui and save hdf5
  • put all setup commands in python script
  • do we need feedback for laser? (no)
  • run at 120Hz  overnight and validate
• resolve vhdl axi-lite offset constants
  • why doesn't offset 0x400000 (which turns into 0xc00000) work?
  • https://forums.xilinx.com/t5/Synthesis/How-to-display-post-synthesis-integer-constant-values/td-p/692285