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changes.mady.by.user Christopher O'Grady

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changes.mady.by.user Sioan Zohar

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  • also needed:
  • under "commands" tab need to ConfigLclsTimingV1.  this controls a multiplexer that routes the evr clock/data to the fpga, either from lcls1 or lcls2

 

Simulation tools

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug937-vivado-design-suite-simulation-tutorial.pdf

(as of 06/21/2018, simulation tools use C library that's only present on RHEL 7 machines.)

 

SURF website

https://slaclab.github.io/surf-doc/surf_1_documentation/html (this website is no longer maintened (6/21/2018) use github link below instead)

https://github.com/slaclab/surf

 

pyrogue python scripting example

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