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- use the vivado core-generator to generate an ila_0 core. Matt says use the generated .xci file, not the .dcp file
- add the .xci file to appropriate ruckus.tcl with something like this:
- loadIpCore -path "$::DIR_PATH/coregen/ila_0.xci"
- instantiate an ila_0 component in vhdl
- build and program the fpga
- open vivado (currently on rdsrv223)
- connect over jtag
- find .ltx file generated by build with ila. this is a list of signals that are exported to the ila.
- in vivado click on the fpga (e.g. xck115_0) in top left
- in the "hardware device properties" enter the .ltx file in the "probes file" field
- a list of ila's should appear along with waveforms in the display
- also needed:
- under "commands" tab need to ConfigLclsTimingV1. this controls a multiplexer that routes the evr clock/data to the fpga, either from lcls1 or lcls2
SURF website
https://slaclab.github.io/surf-doc/surf_1_documentation/html
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