Page History

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• under "commands" tab need to ConfigLclsTimingV1.  this controls a multiplexer that routes the evr clock/data to the fpga, either from lcls1 or lcls2
• under "variables" tab GtLoopback 0 is normal mode, 2 is internal loopback which includes EVG simulator sending some opcodes, 4 is a later loopback as described on page 85 of Xilinx ug576 guide https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf
• mmcm is like a souped-up old dcm (digital clock manager) able to generate many more frequencies using, with jitters ~25ps (comparable to a standard external oscillator)
• each of qsfp1 input 2 (counting from 0) can only accept lcls1 timing (static) and input 3 can only accept lcls2 timing.  Possibly it's switched, but I don't think so.
• in "variables" tab TimeToolDev->HW->TimingCore->EvrCore, sofCount/eofCount/FidCount should all increment at 360Hz if things are working.

Using Xilinx Integrated Logic Analyzer (ILA, aka "ChipScope")

• open vivado (currently on rdsrv223)
• connect over jtag
• find .ltx file generated by build with ila.  this is a list of signals that are exported to the ila.
• in vivado click on the fpga (e.g. xck115_0) in top left
• in the "hardware device properties" enter the .ltx file in the "probes file" field
• a list of ila's should appear along with waveforms in the display