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- pgplanewrapper.vhd has this code:
evrRxP(1) <= qsfp1RxP(3);
evrRxN(1) <= qsfp1RxN(3);evrRxP(0) <= qsfp1RxP(2);
evrRxN(0) <= qsfp1RxN(2);
- not sure why 2 EVRs (maybe lcls1 and lcls2?)
- other 6 lanes are all hooked up to PGP
- pgplanewrapper also hooks up the 6 dmaObMasters/dmaIbMasters etc to the pgp lanes (last two are unused, because they are used by evr)
- timetoolkcu1500.vhd hooks dmaIbMasters(0) to the AxiStreamTap, so our camera data is on qsfp0[0], which is the first of the 6 pgp lanes
- timing fibers are on the last two fibers of qsfp1
Setting Up TimingCore
- under "commands" tab need to ConfigLclsTimingV1
- under "variables" tab GtLoopback 0 is normal mode, 2 is internal loopback which includes EVG simulator sending some opcodes, 4 is a later loopback as described on page 85 of Xilinx ug576 guide https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf
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