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Motivation

Need simple serial interface to ASICs for configuring registers and sending commands that allows for backpressure.

Existing Standards not a good fit

SPI: No backpressure. No way for ASIC to signal that it is done with a command or ready for new data. Requires polling.

I2C: Backpressure possible through clock stretching, but complex protocol and implementation.

SACI Features

Master/Slave Serial Interface

4 Signals

• 3 shared: saciClk, saciCmd, saciRsp
• 1 dedicated select line per slave: saciSelL
• Allows multiple slaves on same SACI bus. (Similar to  SPI.)

Serial data transmitted on rising edge of clock and sampled on falling edge. MSB first.

Toggling saciSelL resets Slave state machine in case of lockup.

Waveforms

Writes

• Master lowers saciSelL
• Master sends Start Bit, Write Bit, Command, Address and Data

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• Slave responds with Start Bit, Write bit, Command and Address
• Master optionally raises saciSelL when done.

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Reads

• Master lowers saciSelL
• Master sends Start Bit, Read Bit, Command and Address

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• Slave responds with Start Bit, Write bit, Command, Address and Data
• Master optionally raises saciSelL when done.

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Contact

Ben Reese

bareese@slac.stanford.edu