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Defines polarity of DTACK_N. If connected to ground, then
DTACK_N is active low. If connected to VDD33, then
DTACK_N is active high.

On FM2000, this pin is permanently used for this function.

On FM3000/FM4000, this pin is sampled at reset to
determine DTACK polarity and can be used as a general
purpose I/O after reset (input by default).

DTACK_INV is pulled down to GND by a 4.7kOhm resistor. 

The PLX doesn't connect to the DTACK_INV pin.

Conclusion:

Statically pulled down.  So this is probably not related to the issue we are dealing with.

Defines polarity of RW_N pin when in EBI mode. When
connected to ground, then read is active high while write is
active low. Conversely, when connected to VDD33, read is
active low while write is active high.
 

On FM2000, this pin is permanently used for this function
 

On FM3000/FM4000, this pin is sampled at reset and can
be used as a general purpose I/O after reset (input by
default).

RW_INV is pulled up to VDD by a 4.7kOhm resistor. 

The PLX doesn't connect to the RW_INV pin.

Conclusion:

Setting this pin to VDD33 will disable parity checking on
incoming write data.
 

On FM2000, this pin is permanently used for this function.
 

On FFM3000/FM4000, this pin is sampled at reset and can
be used as a general purpose I/O after reset (input by
default).

A.K.A. IGN_PAR

IGN_PAR is pulled down to GND by a 4.7kOhm resistor. 

The PLX doesn't connect to the IGN_PAR pin.

Conclusion:

Statically pulled down.  So this is probably not related to the issue we are dealing with.

Used for either SPI or general purpose I/O pins.
 

These pins are used as SPI when the switch retrieves its
configuration from an external SPI EEPROM (if this enabled)
and as GPIO after.

The pin directions when the interface is used as SPI are:
• SPI_CLK: Out
• SPI_CS_N: Out
• SPI_MOSI: Out
• SPI_MISO: In
 

Note: The pin SPI_MOSI was previously called SPI_SO in
the FM2000 and the pin SPI_MISO was called SPI_SI.

At bootup, these pins are GPIO inputs by default (see page 70 of FM4000 datasheet).

The PLX doesn't connect to the any of these   pins.  They are accessible via the debug J8 connector.

Conclusion:

This is only a name change.  Pinout has not changed.  So this is probably not related to the issue we are dealing with.

General purpose I/O pin.

This pin is also latched at reset to determine the parity mode
on the data bus after reset (high=even, low=odd). This pin
must be pulled up or pulled down and cannot be left
unconnected. Pull up for compatibility with FM2000 series
devices.

General purpose I/O pin.

This pin is latched at reset to define DTACK and DATA
behavior. If this pin is pulled up, then DTACK and DATA (if
read) are asserted when needed and remain asserted until
CS is de-asserted. If this pin is pulled down, then DTACK
and DATA are asserted (if read) for one cycle, then DTACK
gets actively de-asserted for one cycle and tri-stated after
that. For compatibility with FM2000 devices, this pin should
be pulled down. It should not be left unconnected.