From Eric Siskind on April 9, 2007:

With current parameters, the combined use of fabric by a PEB
and a PIB is a bit more than 7% of slices in an FX60.  A PEB
currently also uses 5 block RAMs, while a PIB has 3.  A
combined ECB and FLB use around 0.5% of the slices, with 1
block RAM in the ECB and 5 in the FLB.  There are also second
order effects because there is a cross-bar between the PEBs
and the ECBs, and another one between the FLBs and the PIBs.
The actual cross-bar logic lives in the blocks at both ends,
so the size of a PIB (for instance) is dependent upon the
number of FLBs in the system.  As an example, each PIB has a
multiplexer to select a wide word coming from the output of a
FIFO in one of the FLBs.  The more FLBs there are, the greater
the number of inputs to that mux.  Right now, the width of the
mux is 117 bits, and its width grows by 5 bits for each new
bit that you add to the width of the RLDRAM address, so it
will grow to 127 bits when we migrate from 128 to 512
megabytes of RLDRAM. The PIB also has to demultiplex a request
to read a word out of one of these FLB FIFOs to a single
target FLB, and multiplex the grants that it receives in
response.  In addition, the size of the memory controller is
dependent upon the number of PIC blocks instantiated, as there
a multiplexers for both the RLDRAM address and write data that
grow with the number of DMA data sources, as well as lots of
stuff in the memory arbitration and bank select/bank busy
logic that grow at least linearly with the number of PIC
component instantiations.

Of the roughly 25k slices in the FX60, right now I'm burning
around 11,200 for 6 instantiations of the PEB and PIB with
loopback logic between them, another 400 or so for the ECB and
FLB instantiations (3 each), 2,400 for the memory controller,
around 700 in the interfaces between the D-side and I-side
PLBs and the memory controller, around 600 in the Samsung
flash controller (mostly in the R-S encoder/decoder), 100 in
the LED display controller, and around 400-500 in various DCR
control logic and read data multiplexer, interrupt control,
reset logic, and the like.  This is all for the baby CEM with
loopback logic but no user protocol cores on the PMC board
platform that you're (hopefully) playing with now.  In
addition to the 6*(5+3) block RAMs in the PEBs and PIBs and
the 3*(1+5) in the ECBs and FLBs, there are two more in the
OCPRAM, one in the flash page buffer, and (apparently) two
more in the flash R-S decoder, for a total of 71.  The PIB is
also about to grow for two reasons: 1) I left out support for
import messaging in section 4.14(?) of the CEM document
(although this will only be a touch more - primarily another
state or two in an FSM plus another mux on the write data
going to the PIB output transaction FIFO); and 2) Mike wants
to support multiple interleaved data streams on a single PIB,
because Ryan is multiplexing cells from multiple data sources
within one of his flash management chips onto the single PGP
lane from that chip to the Virtex-4.  This latter requirement
means that a single PIB will have to context switch among 4
different incoming DMA streams - each with its own TDE,
descriptor, address counters, length counters, cache line
reformatting logic, and incoming data processing state.  Right
at the moment, I might guess that this is going to add another
400-500 slices plus 2 block RAMs to each PIB instantiation -
or at least to the 4 instantiations for the PGP lanes - so
perhaps another 7-8% of an FX60 in total.