{
    "ltx_root": {
        "version": 4,
        "minor": 0,
        "ltx_data": [
            {
                "name": "EDA_PROBESET",
                "active": true,
                "debug_cores": [
                    {
                        "type": "XSDB_V3",
                        "name": "dbg_hub",
                        "spec": "labtools_xsdbm_v3"
                    },
                    {
                        "type": "VIO_V2",
                        "name": "design_1_i/vio_0",
                        "spec": "labtools_vio_v3",
                        "ipName": "vio",
                        "core_location": {
                            "user_chain": 1,
                            "slave_index": 0,
                            "bscan_switch_index": 0
                        },
                        "uuid": "01A4B5947C445FA6BD66F70F5F031273",
                        "pins": [
                            {
                                "name": "probe_in0",
                                "id": 0,
                                "type": "DATA",
                                "direction": "IN",
                                "isVector": true,
                                "leftIndex": 0,
                                "rightIndex": 3,
                                "portIndex": 0,
                                "nets": [
                                    {
                                        "name": "design_1_i/hwRev_1",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "design_1_i/hwRev_1[3]"
                                            },
                                            {
                                                "name": "design_1_i/hwRev_1[2]"
                                            },
                                            {
                                                "name": "design_1_i/hwRev_1[1]"
                                            },
                                            {
                                                "name": "design_1_i/hwRev_1[0]"
                                            }
                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe_in1",
                                "id": 1,
                                "type": "DATA",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 1,
                                "nets": [
                                    {
                                        "name": "design_1_i/prsntAnalogL_1",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe_in2",
                                "id": 2,
                                "type": "DATA",
                                "direction": "IN",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 2,
                                "nets": [
                                    {
                                        "name": "design_1_i/prsntCarrierL_1",
                                        "isBus": false
                                    }
                                ]
                            },
                            {
                                "name": "probe_in3",
                                "id": 3,
                                "type": "DATA",
                                "direction": "IN",
                                "isVector": true,
                                "leftIndex": 0,
                                "rightIndex": 3,
                                "portIndex": 3,
                                "nets": [
                                    {
                                        "name": "design_1_i/dipSw_1",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "design_1_i/dipSw_1[3]"
                                            },
                                            {
                                                "name": "design_1_i/dipSw_1[2]"
                                            },
                                            {
                                                "name": "design_1_i/dipSw_1[1]"
                                            },
                                            {
                                                "name": "design_1_i/dipSw_1[0]"
                                            }
                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe_in4",
                                "id": 4,
                                "type": "DATA",
                                "direction": "IN",
                                "isVector": true,
                                "leftIndex": 0,
                                "rightIndex": 2,
                                "portIndex": 4,
                                "nets": [
                                    {
                                        "name": "design_1_i/timingIn_1",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "design_1_i/timingIn_1[2]"
                                            },
                                            {
                                                "name": "design_1_i/timingIn_1[1]"
                                            },
                                            {
                                                "name": "design_1_i/timingIn_1[0]"
                                            }
                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe_out0",
                                "id": 5,
                                "type": "DATA",
                                "direction": "OUT",
                                "isVector": false,
                                "leftIndex": 0,
                                "rightIndex": 0,
                                "portIndex": 0,
                                "nets": [
                                    {
                                        "name": "design_1_i/pwrEnable",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "design_1_i/pwrEnable[0]"
                                            }
                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe_out1",
                                "id": 6,
                                "type": "DATA",
                                "direction": "OUT",
                                "isVector": true,
                                "leftIndex": 0,
                                "rightIndex": 3,
                                "portIndex": 1,
                                "nets": [
                                    {
                                        "name": "design_1_i/vio_0_probe_out1",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "design_1_i/vio_0_probe_out1[3]"
                                            },
                                            {
                                                "name": "design_1_i/vio_0_probe_out1[2]"
                                            },
                                            {
                                                "name": "design_1_i/vio_0_probe_out1[1]"
                                            },
                                            {
                                                "name": "design_1_i/vio_0_probe_out1[0]"
                                            }
                                        ]
                                    }
                                ]
                            },
                            {
                                "name": "probe_out2",
                                "id": 7,
                                "type": "DATA",
                                "direction": "OUT",
                                "isVector": true,
                                "leftIndex": 0,
                                "rightIndex": 2,
                                "portIndex": 2,
                                "nets": [
                                    {
                                        "name": "design_1_i/timingOut",
                                        "isBus": true,
                                        "subnets": [
                                            {
                                                "name": "design_1_i/timingOut[2]"
                                            },
                                            {
                                                "name": "design_1_i/timingOut[1]"
                                            },
                                            {
                                                "name": "design_1_i/timingOut[0]"
                                            }
                                        ]
                                    }
                                ]
                            }
                        ]
                    }
                ]
            }
        ]
    }
}