From: "Reese, Benjamin A." <bareese@slac.stanford.edu>
Subject: HPS Front End Board Schematic Update
Date: October 21, 2013 5:18:10 PM PDT
To: "Herbst, Ryan T." <rherbst@slac.stanford.edu>, "Hansson Adrian, Per Ola" <phansson@slac.stanford.edu>, "Ruckman, Larry" <ruckman@slac.stanford.edu>, "Nishimura, Kurtis A." <kurtisn@slac.stanford.edu>

All,
 
I’ve updated the Front End Board schematic with the following changes:
 
Hybrid_pwr Sheets
- HY_AVDD_RTN was mislabeled (HY_AVVD_RTN) at AD5144 pins.
- AD5144 (Digital POT) now attached to FPGA with SPI interface rather than I2C.
- RT9018A Linear Regulators replaced with lower dropout ISL80113 regulators
- Power Good lines from regulators brought back to FPGA pins.
 
Main_power_mon Sheet
- Added 2 board temperature thermistors on XADC channels 14 and 15.
 
Main_power_reg Sheet
- RT9018A Linear Regulators for +3.3V and A+1.8V replaced with ISL80113 regulators.
- Added an AD5144 to allow trimming of step-down voltages. A+1.6V, A+2.9V_DVDD, A+2.9V_DVDD and A+2.2V can now all be trimmed by the FPGA.
- A+1.6V Regulator now has 3x538nH inductors rather than 1x206nH to allow for up to 6A output.
 
https://confluence.slac.stanford.edu/display/ppareg/PC_249_901_07_C00